SALT: Efficient Load-Time Scheduling for Superscalar Processor Families Using Compiler Annotations

Superscalar processors exploit instruction-level parallelism (ILP) by dispatching machine instructions to several functional units where they are executed in parallel. The efficiency of parallelization at run-time can be increased through an additional scheduling phase for a concrete target machine in the compiler. But if the mobile code should be executed in a heterogenous network with processors of one family, the concrete target machine is not known at compile-time. Hence, scheduling must be deferred to a later phase immediately before or during program execution. Recently, we developed a novel approach called CALS 1 [4], which prepares parallelization at compile-time and performs scheduling at load-time of a program. It uses proofcarrying code techniques for scheduling in linear time by using an one-pass algorithm. Additionally, the closely related task of register allocation is split between compile-time and load-time of a program. In this paper, we present the evaluation of our new prototype SALT , which provides outstanding results and offers direct execution of the arranged code after scheduling. Currently, SALT achieves improvements of up to 30.9% compared to simple compilation without scheduling and even outperforms list scheduling by up to 21.8% (4% in average). Furthermore, the size of the annotations could be reduced by 24% in average.